本标准旨在供SoC、ASIC、ASSP和FPGA开发人员或供应商使用，这些开发人员或供应商有意合并具有低信号计数和高数据传输带宽的主接口，以访问符合该接口的多个从设备源。它也适用于有意提供符合本标准的从属设备的外围设备开发商或供应商，包括非易失性存储器、易失性存储器、图形外围设备、网络外围设备、FPGA、传感器等。项目1775.59和19-395。

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.59 and 19-395.